Nhiều chương trình CAD hiện nay cho phép tạo ra các mô hình ba chiều để có thể nhìn từ mọi góc độ. Các chương trình CAD mô hình hóa vật thể đặc tiên tiến là một hệ thống thiết kế hiện thực ảo. Những mô hình đặc như vậy có thể được dùng làm cơ sở cho các phân tích phần tử hữu hạn (FEA) và / hoặc tính toán động lực dòng chảy (CFD) của thiết kế. Cho đến ứng dụng gia công với trợ giúp máy tính (CAM), những mô hình này cũng có thể được dùng. | Complementary high-speed SiGe and CMOS buffers 239 design effort whereas the second choice includes an increased IC area high design effort and resistive losses from parasitics. These considerations therefore suggest use of the third alternative where a feedback network is used to swap amplifier gain for a wideband frequency response. Advantageously this stabilizes gain and port impedances as well and this well-known technology is compatible with low-cost integration in digital CMOS. However the amount of applicable feedback is limited by stability considerations and this has traditionally been dealt with by using different compensation networks which aim at incresing the amount of available stable feedback. Conventional microwave feedback designs use complex compensating capacitor networks for the purpose but this approach is area-consuming sensitive to parasitics and time-consuming to design. An example of a very complex feedback network is seen in Fig. 13 a which is the single-stage UWB low-noise amplifier LNA design reported by Zhan Taylor 2006 . This high-performance low-noise amplifier LNA in 90-nm CMOS achieved inspiring performance with a best possible NF dB performance over the UWB bands. However this particular implementation uses a supply voltage and is therefore really not applicable for designs in standard digital CMOS as these use for 130-nm and as low as supplies for newer process nodes as its use of stacked transistors limits the available dynamic range DR and its complex feedback network requires an involved design effort. Fundamentally limiting is the low intrinsic gain of digital transistors which decreases a single stage gain to an unacceptably low level. A possible alternative which uses three cascaded gain stages is shown in Fig. 13 b as reported by Janssens et al. 1997 where the main idea is to improve isolation of the circuit by driving a resistive feedback network with a gain stage. The circuit in Fig. 13 b is in fact
