Standardized Functional Verification- P15:Every manager who brings a design to tape-out or who purchases IP must eventually face these questions. The ability to answer these questions based on quantitative analysis is both vital and yet elusive. In spite of the enormous technical advances made in IC development and verification software, the answers to these questions are still based largely on guesswork and hand waving. | Factors to consider in using Convergence 125 Fig. . Stratification of convergence Another factor to consider is which RTL-based coverage measure to use in computing the test generator s power using the convergence technique. The greater the granularity in the measure such as using expression coverage instead of line coverage the better indicator the convergence is likely to be of the test generator s power. Investigating the empirical results for a given project or multiple projects will provide insight in the best way to estimate power with convergence. line convergence state convergence arc convergence expression convergence y increasing granularity Fig. . Determining convergence of test generator against a target 126 Chapter 5 - Normalizing Data Another effect might require some adjustments in how one calculates convergence an initial step function in coverage from running a handful of tests. In such a case one might consider the level achieved by the initial step function as the baseline from which the exponential growth curve rises. Complexity of a Target Complexity Z is proportional to the amount of logic to be exercised in the target. Many different measures have been proposed and used to model the complexity of computer code such as lines of uncommented code but for the purposes of functional verification of an IC it s more useful to consider a more reasonable measure a particular count of the number of gates in the target. A common practice in the IC design community is the division of logic into datapath logic and control logic. Datapath logic usually consists of uniform arrays of cells such as bits in a register file slices in an adder and so on. The remaining logic is regarded as control logic because it of course exerts control over the datapath telling it what to do . It s widely known that the vast majority of bugs in a design are associated with the control logic rather than the datapath logic. It stands to reason hence our reasonable
