Handbook of Algorithms for Physical Design Automation part 86 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 832 Handbook of Algorithms for Physical Design Automation FIGURE Coarse-grained power gating with macro core. GND Ground VDD voltage drain drain VGND virtual ground. Fine-grained power gating as shown in Figure where the footer switches are implemented within the logic in a regular layout are more desirable in a high-performance design where the voltage drop across the power gate as well as IR and EM electromigration requirements are more stringent. INTO THE FUTURE We have summarized the current workings of IBM s physical synthesis capabilities to display the complexities of such a system. Physical synthesis requires a seamless integration of many previously separate design automation domains such as optimization placement timing extraction and routing. However as technology progresses toward 45 nm and beyond more will be demanded of physical synthesis. It must be dynamic and must constantly adapt to changing technologies design styles and design specifications. Timing closure will continue to evolve into the even more complex problem of design closure. Design closure requires that accurate modeling of the clock tree network and routing be incorporated earlier and earlier up the physical synthesis pipeline to take into account their effects on timing and signal integrity. Meeting global power constraints using multithreshold voltages voltage islands power gating etc. also becomes more critical. One must pay attention to how physical-design choices relate to chip fabrication so design for manufacturability and handling of variability will become increasingly important. Optimizations must become more sophisticated to take these additional objectives into account. Increasing chip sizes and additional requirements for physical synthesis to meet and incorporate these additional constraints also further exacerbates the ability to run efficiently perhaps another reason why hierarchical design is becoming more prevalent. FIGURE Fine-grained power .
