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Petri Net Part 3

Tham khảo tài liệu 'petri net part 3', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | Petri Net Based Modelling of Communication in Systems on Chip 51 iterative solution but is centred on simulation. In principle it is possible to generate an ordinary Petri Net with the same functionality as a CPN that can then in turn be solved analytically. Due to the complex data structures coloursets and transfer functions included in a CPN the equation system describing such an underlying Petri Net would be very large. Model parameters can be measured by definition of monitors that collect data relating to different parts of the CPN such as occupation of places or the number of times a specific transition fires. The markup language used for model description also allows to use more complex monitors including for example conditional data collection. 3. Petri net modelling of exemplary communication scenarios In this section the exemplary application of Petri Nets for modelling communication scenarios is presented. The modelling possibilities span from simple bus based processor communication scenarios to complex NoC examples. 3.1 DSPN based processor communication model The TMS320C6416 Texas Instruments 2007 see Fig. 9 is a high performance digital signal processor DSP based on a VLIW-architecture. This DSP features a couple of interfaces an Enhanced DMA-controller EDMA handling data transfers and two dedicated coprocessors Viterbi and Turbo decoder coprocessor . Exemplary communication scenarios on this DSP have been modelled. The C6416 TEB Test Evaluation Board platform including the C6416 DSP has been utilized to measure parameters of these modelled communication scenarios described in the following. Thus modelling results have been proved and verified by comparison with measured values. Fig. 9. Basic block diagram of the TMS320C6416 DSP In Fig. 10 a block diagram of the C6416 and different communication paths of basic communication processes and are depicted. In the first scenario two operators compete for one critical resource the external memory interface