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báo cáo hóa học:" Research Article FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264/AVC"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264/AVC | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2009 Article ID 893897 16 pages doi 10.1155 2009 893897 Research Article FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264 AVC Obianuju Ndili and Tokunbo Ogunfunmi Department of Electrical Engineering Santa Clara University Santa Clara CA 95053 USA Correspondence should be addressed to Tokunbo Ogunfunmi togunfunmi@scu.edu Received 21 March 2009 Revised 18 June 2009 Accepted 27 October 2009 Recommended by Ahmet T. Erdogan There is an increasing need for high quality video on low power portable devices. Possible target applications range from entertainment and personal communications to security and health care. While H.264 AVC answers the need for high quality video at lower bit rates it is significantly more complex than previous coding standards and thus results in greater power consumption in practical implementations. In particular motion estimation ME in H.264 AVC consumes the largest power in an H.264 AVC encoder. It is therefore critical to speed-up integer ME in H.264 AVC via fast motion estimation FME algorithms and hardware acceleration. In this paper we present our hardware oriented modifications to a hybrid FME algorithm our architecture based on the modified algorithm and our implementation and prototype on a PowerPC-based Field Programmable System on Chip FPSoC . Our results show that the modified hybrid FME algorithm on average outperforms previous state-of-the-art FME algorithms while its losses when compared with FSME in terms of PSNR performance and computation time are insignificant. We show that although our implementation platform is FPGA-based our implementation results compare favourably with previous architectures implemented on ASICs. Finally we also show an improvement over some existing architectures implemented on FPGAs. Copyright 2009 O. Ndili and T. Ogunfunmi. This is an open access article distributed under the Creative Commons Attribution