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EURASIP Journal on Applied Signal Processing 2003:6, 502–513 c 2003 Hindawi Publishing

EURASIP Journal on Applied Signal Processing 2003:6, 502–513 c 2003 Hindawi Publishing Corporation Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications Kimmo Kuusilinna Tampere University of Technology, Korkeakoulunkatu 1, P.O. Box. 553, FIN-33101, Tampere, Finland University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: kimmo.kuusilinna@tut.fi Chen Chang University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: chenzh@eecs.berkeley.edu M. Josephine Ammer University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: mjammer@eecs.berkeley.edu Brian C. Richards University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston. | EURASIP Journal on Applied Signal Processing 2003 6 502-513 2003 Hindawi Publishing Corporation Designing BEE A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications Kimmo Kuusilinna Tampere University of Technology Korkeakoulunkatu 1 P.O. Box. 553 FIN-33101 Tampere Finland University of California Berkeley Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 USA Email kimmo.kuusilinna@tut.fi Chen Chang University of California Berkeley Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 USA Email chenzh@eecs.berkeley.edu M. Josephine Ammer University of California Berkeley Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 USA Email mjammer@eecs.berkeleyedu Brian C. Richards University of California Berkeley Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 USA Email richards@eecs.berkeley.edu Robert W. Brodersen University of California Berkeley Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 USA Email rb@eecs.berkeley.edu Received 28 February 2002 and in revised form 10 October 2002 This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verily that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz. Keywords and phrases rapid prototyping FPGA .