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Bài giảng Computer Architecture: Chapter 3.1 - Prof. Jerry Breecher

| Computer Architecture Chapter 3 Instruction-Level Parallelism I Prof. Jerry Breecher CSCI 240 Fall 2003 Chap. 3 -ILP 1 Chapter Overview 3.1 Instruction Level Parallelism: Concepts and Challenges 3.2 Overcoming Data Hazards with Dynamic Scheduling 3.3 Dynamic Scheduling: Examples & The Algorithm 3.4 Reducing Branch Penalties with Dynamic Hardware Prediction 3.5 High Performance Instruction Delivery 3.6 Taking Advantage of More ILP with Multiple Issue 3.7 Hardware-based Speculation 3.8 Studies of The Limitations of ILP 3.10 The Pentium 4 Chap. 3 -ILP 1 Ideas To Reduce Stalls Chapter 3 Chapter 4 Chap. 3 -ILP 1 Instruction Level Parallelism ILP is the principle that there are many instructions in code that don’t depend on each other. That means it’s possible to execute those instructions in parallel. This is easier said than done: Issues include: Building compilers to analyze the code, Building hardware to be even smarter than that code. This section looks at some of the . | Computer Architecture Chapter 3 Instruction-Level Parallelism I Prof. Jerry Breecher CSCI 240 Fall 2003 Chap. 3 -ILP 1 Chapter Overview 3.1 Instruction Level Parallelism: Concepts and Challenges 3.2 Overcoming Data Hazards with Dynamic Scheduling 3.3 Dynamic Scheduling: Examples & The Algorithm 3.4 Reducing Branch Penalties with Dynamic Hardware Prediction 3.5 High Performance Instruction Delivery 3.6 Taking Advantage of More ILP with Multiple Issue 3.7 Hardware-based Speculation 3.8 Studies of The Limitations of ILP 3.10 The Pentium 4 Chap. 3 -ILP 1 Ideas To Reduce Stalls Chapter 3 Chapter 4 Chap. 3 -ILP 1 Instruction Level Parallelism ILP is the principle that there are many instructions in code that don’t depend on each other. That means it’s possible to execute those instructions in parallel. This is easier said than done: Issues include: Building compilers to analyze the code, Building hardware to be even smarter than that code. This section looks at some of the problems to be solved. 3.1 Instruction Level Parallelism: Concepts and Challenges 3.2 Overcoming Data Hazards with Dynamic Scheduling 3.3 Dynamic Scheduling: Examples & The Algorithm 3.4 Reducing Branch Penalties with Dynamic Hardware Prediction 3.5 High Performance Instruction Delivery 3.6 Taking Advantage of More ILP with Multiple Issue 3.7 Hardware-based Speculation 3.8 Studies of The Limitations of ILP 3.10 The Pentium 4 Chap. 3 -ILP 1 Terminology Instruction Level Parallelism Basic Block - That set of instructions between entry points and between branches. A basic block has only one entry and one exit. Typically this is about 6 instructions long. Loop Level Parallelism - that parallelism that exists within a loop. Such parallelism can cross loop iterations. Loop Unrolling - Either the compiler or the hardware is able to exploit the parallelism inherent in the loop. Chap. 3 -ILP 1 Basic Block (BB) ILP is quite small BB: a straight-line code sequence with no branches in except to