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Logic Synthesis With Verilog HDL part 4

[ Team LiB ] 14.5 Verification of Gate-Level Netlist The optimized gate-level netlist produced by the logic synthesis tool must be verified for functionality. Also, the synthesis tool may not always be able to meet both timing and area requirements if they are too stringent. | Team LiB 14.5 Verification of Gate-Level Netlist The optimized gate-level netlist produced by the logic synthesis tool must be verified for functionality. Also the synthesis tool may not always be able to meet both timing and area requirements if they are too stringent. Thus a separate timing verification can be done on the gate-level netlist. 14.5.1 Functional Verification Identical stimulus is run with the original RTL and synthesized gate-level descriptions of the design. The output is compared to find any mismatches. For the magnitude comparator a sample stimulus file is shown below. Example 14-3 Stimulus for Magnitude Comparator module stimulus reg 3 0 A B wire A_GT_B A_LT_B A_EQ_B Instantiate the magnitude comparator magnitude_comparator MC A_GT_B A_LT_B A_EQ_B A B initial monitor time A b B b A_GT_B b A_LT_B b A_EQ_B b A B A_GT_B A_LT_B A_EQ_B stimulate the magnitude comparator. initial begin A 4 b1010 B 4 b1001 10 A 4 b1110 B 4 b1111 10 A 4 b0000 B 4 b0000 10 A 4 b1000 B 4 b1100 10 A 4 b0110 B 4 b1110 10 A 4 b1110 B 4 b1110 end endmodule The same stimulus is applied to both the RTL description in Example 14-1 and the synthesized gate-level description in Example 14-2 and the simulation output is compared for mismatches. However there is an additional consideration. The gate-level description is in terms of library cells VAND VNAND etc. Verilog simulators do not understand the meaning of these cells. Thus to simulate the gate-level description a simulation library abc_100.v must be provided by ABC Inc. The simulation library must describe cells VAND VNAND etc. in terms of Verilog HDL primitives and nand etc. For example the VAND cell will be defined in the simulation library as shown in Example 14-4. Example 14-4 Simulation Library Simulation Library abc_100.v. Extremely simple. No timing checks. module VAND out in0 in1 input in0 input in1 output out timing information rise fall and min typ max specify in0 out 0.260604 0.513000 0.955206 0.255524 0.503000 .