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Logic Synthesis With Verilog HDL part 5

[ Team LiB ] 14.7 Example of Sequential Circuit Synthesis In Section 14.4.2, An Example of RTL-to-Gates, we synthesized a combinational circuit. Let us now consider an example of sequential circuit synthesis. Specifically, we will design finite state machines. 14.7. | Team LiB 14.7 Example of Sequential Circuit Synthesis In Section 14.4.2 An Example of RTL-to-Gates we synthesized a combinational circuit. Let us now consider an example of sequential circuit synthesis. Specifically we will design finite state machines. 14.7.1 Design Specification A simple digital circuit is to be designed for the coin acceptor of an electronic newspaper vending machine. Assume that the newspaper cost 15 cents. Wow Who gives that kind of a price any more Well let us assume that it is a special student edition The coin acceptor takes only nickels and dimes. Exact change must be provided. The acceptor does not return extra money. Valid combinations including order of coins are one nickel and one dime three nickels or one dime and one nickel. Two dimes are valid but the acceptor does not return money. This digital circuit can be designed by using the finite state machine approach. 14.7.2 Circuit Requirements We must set some requirements for the digital circuit. When each coin is inserted a 2-bit signal coin 1 0 is sent to the digital circuit. The signal is asserted at the next negative edge of a global clock signal and stays up for exactly 1 clock cycle. The output of the digital circuit is a single bit. Each time the total amount inserted is 15 cents or more an output signal newspaper goes high for exactly one clock cycle and the vending machine door is released. A reset signal can be used to reset the finite state machine. We assume synchronous reset. 14.7.3 Finite State Machine FSM We can represent the functionality of the digital circuit with a finite state machine. input 2-bit coin 1 0 no coin x0 2 b00 nickel x5 2 b01 dime x10 2 b10. output 1-bit newspaper release door when newspaper 1 b1 states 4 states s0 0 cents s5 5 cents s10 10 cents s15 15 cents The bubble diagram for the finite state machine is shown in Figure 14-10. Each arc in the FSM is labeled with a label input output where input is 2-bit and output is 1-bit. For example x5 0 means