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Useful Modeling Techniques part 4

Procedural continuous assignments can be used to override the assignments on registers and nets. assign and deassign can override assignments on registers. force and release can override assignments on registers and nets. assign and deassign are used in the actual design. | Team LiB 9.6 Summary In this chapter we discussed the following aspects of Verilog Procedural continuous assignments can be used to override the assignments on registers and nets. assign and deassign can override assignments on registers. force and release can override assignments on registers and nets. assign and deassign are used in the actual design. force and release are used for debugging. Parameters defined in a module can be overridden with the defparam statement or by passing a new value during module instantiation. During module instantiation parameter values can be assigned by ordered list or by name. It is recommended to use parameter assignment by name. Compilation of parts of the design can be made conditional by using the ifdef ifndef elsif else and endif directives. Compilation flags are defined at compile time by using the define statement. Execution is made conditional in Verilog simulators by means of the test plusargs system task. The execution flags are defined at run time by flag_name . Up to 30 files can be opened for writing in Verilog. Each file is assigned a bit in the multichannel descriptor. The multichannel descriptor concept can be used to write to multiple files. The IEEE Standard Verilog Hardware Description Language document describes more advanced ways of doing file I O. Hierarchy can be displayed with the m option in any display statement. Strobing is a way to display values at a certain time or event after all other statements in that time unit have executed. Random numbers can be generated with the system task random. They are used for random test vector generation. random task can generate both positive and negative numbers. Memory can be initialized from a data file. The data file contains addresses and data. Addresses can also be specified in memory initialization tasks. Value Change Dump is a popular format used by many designers for debugging with postprocessing tools. Verilog allows all or selected module variables to be .