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Verilog Programming part 2

Trends in HDLs The speed and complexity of digital circuits have increased rapidly. Designers have responded by designing at higher levels of abstraction. | 1.6 Trends in HDLs The speed and complexity of digital circuits have increased rapidly. Designers have responded by designing at higher levels of abstraction. Designers have to think only in terms of functionality. EDA tools take care of the implementation details. With designer assistance EDA tools have become sophisticated enough to achieve a close-to-optimum implementation. The most popular trend currently is to design in HDL at an RTL level because logic synthesis tools can create gate-level netlists from RTL level design. Behavioral synthesis allowed engineers to design directly in terms of algorithms and the behavior of the circuit and then use EDA tools to do the translation and optimization in each phase of the design. However behavioral synthesis did not gain widespread acceptance. Today RTL design continues to be very popular. Verilog HDL is also being constantly enhanced to meet the needs of new verification methodologies. Formal verification and assertion checking techniques have emerged. Formal verification applies formal mathematical techniques to verify the correctness of Verilog HDL descriptions and to establish equivalency between RTL and gatelevel netlists. However the need to describe a design in Verilog HDL will not go away. Assertion checkers allow checking to be embedded in the RTL code. This is a convenient way to do checking in the most important parts of a design. New verification languages have also gained rapid acceptance. These languages combine the parallelism and hardware constructs from HDLs with the object oriented nature of C . These languages also provide support for automatic stimulus creation checking and coverage. However these languages do not replace Verilog HDL. They simply boost the productivity of the verification process. Verilog HDL is still needed to describe the design. For very high-speed and timing-critical circuits like microprocessors the gate-level netlist provided by logic synthesis tools is not optimal. In such .