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Verilog Programming part 4

Two kinds of design methodologies are used for digital design: top-down and bottom-up. A combination of these two methodologies is used in today's digital designs. | Team LiB 2.7 Summary In this chapter we discussed the following concepts. Two kinds of design methodologies are used for digital design top-down and bottom-up. A combination of these two methodologies is used in today s digital designs. As designs become very complex it is important to follow these structured approaches to manage the design process. Modules are the basic building blocks in Verilog. Modules are used in a design by instantiation. An instance of a module has a unique identity and is different from other instances of the same module. Each instance has an independent copy of the internals of the module. It is important to understand the difference between modules and instances. There are two distinct components in a simulation a design block and a stimulus block. A stimulus block is used to test the design block. The stimulus block is usually the top-level block. There are two different styles of applying stimulus to a design block. The example of the ripple carry counter explains the step-by-step process of building all the blocks required in a simulation. This chapter is intended to give an understanding of the design process and how Verilog fits into the design process. The details of Verilog syntax are not important at this stage and will be dealt with in later chapters. Team LiB Team LiB 2.8 Exercises 1 An interconnect switch IS contains the following components a shared memory MEM a system controller SC and a data crossbar Xbar . a. Define the modules MEM SC and Xbar using the module endmodule keywords. You do not need to define the internals. Assume that the modules have no terminal lists. b. Define the module IS using the module endmodule keywords. Instantiate the modules MEM SC Xbar and call the instances meml scl and xbarl respectively. You do not need to define the internals. Assume that the module IS has no terminals. c. Define a stimulus block Top using the module endmodule keywords. Instantiate the design block IS and call the instance .