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Verilog Programming part 28

Overriding Parameters Parameters can be defined in a module definition, as was discussed earlier in Section 3.2.8, Parameters. However, during compilation | 9.2 Overriding Parameters Parameters can be defined in a module definition as was discussed earlier in Section 3.2.8 Parameters. However during compilation of Verilog modules parameter values can be altered separately for each module instance. This allows us to pass a distinct set of parameter values to each module during compilation regardless of predefined parameter values. There are two ways to override parameter values through the defparam statement or through module instance parameter value assignment. 9.2.1 defparam Statement Parameter values can be changed in any module instance in the design with the keyword defparam. The hierarchical name of the module instance can be used to override parameter values. Consider Example 9-2 which uses defparam to override the parameter values in module instances. Example 9-2 Defparam Statement Define a module hello_world module hello_world parameter id_num 0 define a module identification number 0 initial display the module identification number display Displaying hello_world id number d id_num endmodule define top-level module module top change parameter values in the instantiated modules Use defparam statement defparam w1.id_num 1 w2.id_num 2 instantiate two hello_world modules hello_world w1 hello_world w2 endmodule In Example 9-2 the module hello_world was defined with a default id_num 0. However when the module instances w1 and w2 of the type hello_world are created their id_num values are modified with the defparam statement. If we simulate the above design we would get the following output Displaying hello_world id number 1 Displaying hello_world id number 2 Multiple defparam statements can appear in a module. Any parameter can be overridden with the defparam statement. The defparam construct is now considered to be a bad coding style and it is recommended that alternative styles be used in Verilog HDL code. Note that the module hello_world can also be defined using an ANSI C style parameter declaration. Figure 9-3 .