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Bài giảng vi điều khiển - Bài số 5

Microcontroller Instruction Set For interrupt response time information, refer to the hardware description chapter. | Microcontroller Instruction Set For interrupt response time information refer to the hardware description chapter. Instructions that Affect Flag Settings 1 __ Instruction Flag Instruction Flag C OV AC C OV AC ADD X X X CLR C O ADDC X X X CPL C X SUBB X X X ANL C bit X MUL O X ANL C bit X DIV O X ORL C bit X DA X ORL C bit X RRC X MOV C bit X RLC X CJNE X SETB C 1 Note 1. Operations on SFR byte address 208 or bit addresses 209-215 that is the PSW or bits in the PSW also affect flag settings. imEL Instruction Set The Instruction Set and Addressing Modes Rn Register R7-R0 of the currently selected Register Bank. direct 8-bit internal data location s address. This could be an Internal Data RAM location 0-127 or a SFR i.e. I O port control register status register etc. 128-255 . @Ri 8-bit internal data RAM location 0-255 addressed indirectly through register R1or R0. data 8-bit constant included in instruction. data 16 16-bit constant included in instruction. addr 16 16-bit destination address. Used by LCALL and LJMP A branch can be anywhere within the 64K byte Program Memory address space. addr11 11-bit destination address. Used by ACALL and AJMP The branch will be within the same 2K byte page of program memory as the first byte of the following instruction. rel Signed two s complement 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to 127 bytes relative to first byte of the following instruction. bit Direct Addressed bit in Internal Data RAM or Special Function Register. 0509B-B-12 97 jiimEL 2-71 iiimEL Instruction Set Summary 0 1 2 3 4 5 6 7 0 NOP JBC bit rel 3B 2C JB bit rel 3B 2C JNB bit rel 3B 2C JC rel 2B 2C JNC rel 2B 2C JZ rel 2B 2C JNZ rel 2B 2C 1 AJMP P0 2B 2C ACALL P0 2B 2C AJMP P1 2B 2C ACALL P1 2B 2C AJMP P2 2B 2C ACALL P2 2B 2C AJMP P3 2B 2C ACALL P3 2B 2C 2 LJMP addr16 3B 2C LCALL addr16 3B 2C RET 2C RETI 2C ORL dir A 2B ANL dir A 2B XRL dir a 2B ORL C bit 2B 2C 3 RR A RRC A RL A RLC A ORL dir data 3B 2C ANL