Tham khảo tài liệu 'handbook of high temperature superconductor electronics part 10', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 9 High-Temperature Superconducting Digital Circuits Mutsuo Hidaka NEC Corporation Ibaraki Japan INTRODUCTION Superconducting digital circuits have two advantages compared with their competitive semiconductor circuits such as Josephson junctions and superconducting microstrip transmission lines. The Josephson junction can switch its zero-voltage state to a finite-voltage one within a few picoseconds and power dissipation of the switching is extremely low because the voltage state is less than a few millivolts. The superconducting microstrip transmission line is able to transfer picosecond waveforms over virtually any interchip distance with a speed approaching that of light and low attenuation and dispersion. Superconducting microstrip lines can be laid out densely because there is little cross-talk between them and the junctions can be impedance matched with the strip lines to ensure the ballistic transfer of the generated waveforms along the lines. There have been many efforts to develop circuits for exploring the advantages of ultrahigh-speed processing system by superconducting digital circuits using metallic superconductor materials such as Pb and Nb. Two examples of these efforts are the IBM project 1969-1983 1 and the Japanese MITI project 1981-1991 2 . Successful demonstrations for the low-Tc superconductor LTS circuits have been made such as a 4-kbit RAM that has 42 000 junctions and operates at 620 MHz 3 and a computer-communication-network logic circuit that Copyright 2003 by Marcel Dekker Inc. All Rights Reserved. has 4300 junctions and operates at 2 GHz 4 . It has nevertheless become clear that the first-generation superconducting digital circuits so-called latching logic circuits using the zero- and a finite-voltage states for logical 0 and 1 states cannot compete with high-speed semiconductor circuits after paying their cooling penalty. The main drawback of the latching logic is that it is clocked by large radio-frequency RF current from outside .
