Mobile Robots - Moving Intelligence Part 5

Tham khảo tài liệu 'mobile robots - moving intelligence part 5', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | A Reusable UART IP Design and its Application in Mobile Robots 151 Fig. 5. Functional block-diagram of the UART receiver. Fig. 6. SM chart for UART receiver. 152 Mobile Robots moving intelligence Fig. 6 illustrates the SM chart of the UART receiver. The state machine is the Mealy machine and composed of three states idle start_detected and recv_data . Two counters are used. ct1 counts the number of bclkx8 clocks. ct2 counts the number of bits received after the start bit. In the idle state the SM waits for the start bit and then goes to the stsrt_detected state. The SM waits for the rising edge of bclkx8 and then samples rxd again. Since the start bit should be 0 for eight bclkx8 clocks we should read 0 . ct1 is still 0 so ct1 is incremented and the SM waits for bclkx8f. If rxd 1 this is an error condition and the SM clears ct1 and resets to the idle state. Otherwise the SM keeps looping. When rxd is 0 for the fourth time ct1 3 so ct1 is cleared and the state goes to recv_data state. In this state the SM increments ct1 after every rising edge of bclkx8. After the eighth clock ct1 7 and ct2 is checked. If it is not 8 the current value of rxd is shifted in to RSR ct2 is incremented and ct1 is cleared. If ct2 8 all 8 bits have been read and we should be in the middle of the stop bit. If rxd 0 the stop bit has not been detected properly the SM clear ct1 and ct2 and resets to the idle state. If no errors have occurred RDR is loaded from RSR and two counters are cleared and ok_en is set to indicate that the receive operation is completed. The simulation result of the UART receiver receiving 0x53 is shown in Fig. 7. Fig. 7. UART receiver receiving 0x53. Transmitter Module The transmitter circuitry converts a parallel data word into serial form and appends the start parity and stop bits. The transmitter of UART is composed of transmitted bit counter a data shift register a state machine and support logic. Fig. 8 illustrates the functional block diagram of the UART .