Tham khảo tài liệu 'advances in solid state part 2', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | CMOS Nonlinear Signal Processing Circuits 21 shows the rank-order function whereas Fig. 22 b shows the function of the k-WTA. On the average the accuracy of whole circuit was approximated 150 mV. The performance of the chip was degraded by many factors such as the mismatch in comparator cells the different capacitance at input terminals of the evaluation cells and the clock feed-through error. Due to these non-ideal effects each rank-order function was finished in 20 gs. After increasing supply voltage up to V and proper biasing voltage Vfras adjusting the performance of the circuit can be improved. Including power consumption of the input output pads the static power consumption of the chip was mW. Many factors such as precision speed process variation and chip area must be considered for design of a low-power low-voltage rank order extractor. 1. Limitations of low voltage and low power The average power consumption of the circuit is expressed by P P . P . P. . dynamic static short _ current fCV2D Io Ileakage VDD Qsc f VDD 11 where f is the frequency C is the capacitance in the circuit VDD is the voltage supply Io is the standby current Ileakage is the leakage current and the Qsc is the short-current charge during the clock transient period. In order to reduce the power consumption the voltage supply VDD must be reduced and the standby current in the comparator and evaluation cell must be designed as small as possible. In mask layout the clock and its complementary are generated locally to reduce delay and mismatch. Thus the probability of a short current occurring in the circuit is minimized. 2. Speed and precision The accuracy of the comparators determines the resolution of the circuit. For the comparator design the smallest differential voltage that is distinguished correctly is influenced by two factors. One is the charge-injection error in analog switches and the other is the parasitic capacitor Cp effect. The effect is reduced by enlarging the .
