Báo cáo hóa học: " Research Article An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2011 Article ID 790265 15 pages doi 2011 790265 Research Article An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing Christos Ttofis 1 Agathoklis Papadopoulos 1 Theocharis Theocharides 1 Maria K. Michael 1 and Demosthenes Doumenis2 1KIOS Research Center Department of ECE University of Cyprus 1678 Nicosia Cyprus 2SignalGeneriX Ltd 3504 Limassol Cyprus Correspondence should be addressed to Christos Ttofis Received 28 July 2010 Revised 8 January 2011 Accepted 15 January 2011 Academic Editor Neil Bergmann Copyright 2011 Christos Ttofis et al. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. QAM is a widely used multilevel modulation technique with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraints of emerging applications. This work presents the architecture of a highly parallel QAM modulator using MPSoC-based design flow and design methodology which offers multirate modulation. The proposed MPSoC architecture is modular and provides dynamic reconfiguration of the QAM utilizing on-chip interconnection networks offering high data rates more than 1 Gbps even at low modulation levels 16-QAM . Furthermore the proposed QAM implementation integrates a hardware-based resource allocation algorithm that can provide better throughput and fault tolerance depending on the on-chip interconnection network congestion and run-time faults. Preliminary results from this work have been published in the Proceedings of the 18th IEEE IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2010 . The current version of the work includes a detailed description

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