Tuyển tập các báo cáo nghiên cứu về sinh học được đăng trên tạp chí sinh học Journal of Biology đề tài: Research Article Efficient Lookup Table-Based Adaptive Baseband Predistortion Architecture for Memoryless Nonlinearity | Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2010 Article ID 379249 10 pages doi 2010 379249 Research Article Efficient Lookup Table-Based Adaptive Baseband Predistortion Architecture for Memoryless Nonlinearity Seydou N. Ba 1 Khurram Waheed 2 and G. Tong Zhou1 1 School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 USA 2 RF-CMOS Radio Design Group of the Wireless Terminals Business Unit Texas Instruments Inc. Dallas TX 75243 USA Correspondence should be addressed to Seydou N. Ba seydou@ Received 24 November 2009 Revised 23 March 2010 Accepted 14 May 2010 Academic Editor Markus Rupp Copyright 2010 Seydou N. Ba et al. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. Digital predistortion is an effective means to compensate for the nonlinear effects of a memoryless system. In case of a cellular transmitter a digital baseband predistorter can mitigate the undesirable nonlinear effects along the signal chain particularly the nonlinear impairments in the radiofrequency RF amplifiers. To be practically feasible the implementation complexity of the predistorter must be minimized so that it becomes a cost-effective solution for the resource-limited wireless handset. This paper proposes optimizations that facilitate the design of a low-cost high-performance adaptive digital baseband predistorter for memoryless systems. A comparative performance analysis of the amplitude and power lookup table LUT indexing schemes is presented. An optimized low-complexity amplitude approximation and its hardware synthesis results are also studied. An efficient LUT predistorter training algorithm that combines the fast convergence speed of the normalized least mean squares NLMSs with a small hardware footprint is proposed. Results
