Tham khảo tài liệu 'mobile and wireless communications network layer and circuit level design 2012 part 10', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 261 Fully Integrated CMOS Low-Gain-Wide-Range GHz Phase Locked Loop for LR-WPAN Applications 7. Conclusion After arrival on the market in recent years of several wireless local area networks such as WiFi Bluetooth HYPERLAN and so on news technology also appears promising a bright commercial future for both applications in public domain such as those related to home automation and for more related field wireless communications in industrial environments such as the ZigBee network. This WPAN network differs from its two main competitors previously cited from its simplicity of implementation and its low power consumption. ZigBee technology coupled with the IEEE standard offers simple protocol which can be declined in several versions depending on the requirement and the desired topology for purposes of low data rate and weak of use of the medium. This article demonstrates the feasibility of high performance frequency synthesizer for this purpose. The accuracy of the output frequency is guaranteed by the low gain of the VCO without penalizing the time response lock time nor the frequency operating range. The design has been implemented on low cost standard CMOS technology. The proposed topology allows to realize much lower gain if it is required with a very simple calibration method. 8. References Alliance ZigBee. http standard . Bhattacharjee J. Mukherjee D. Laskar J. 2002 . A monolithic CMOS VCO for wireless LAN applications. IEEE International Symposium on Circuits and Systems 3 III-441 -III-444. Chen . 2000 . The VLSI handbook. CRC Press. Choi P. Park H. Kim S. Park S. Nam I. Kim T. et al. 2003 . An experimental coin-sized radio for extremely low-power WPAN IEEE application at GHz. IEEE Journal of Solid State Circuits 38 12 2258-2268. Crols J. Steyaert M. 1995 . A single chip 900 MHz CMOS receiver front-end with a high performance low-IF topology. IEEE Journal of Solid State Circuits 30 12 1483-1492. Gray P. .
