Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2009 Article ID 507426 6 pages doi 2009 507426 Research Article An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator Vinay Sriram and David Kearney University of South Australia Reconfigurable computing Laboratory School of Computer and Information Science Mawson Lakes Campus Adelaide SA 5085 Australia Correspondence should be addressed to Vinay Sriram srivb001@ Received 20 August 2008 Revised 16 February 2009 Accepted 21 April 2009 Recommended by Miriam Leeser Recent times have witnessed an increase in use of high-performance reconfigurable computing for accelerating large-scale simulations. A characteristic of such simulations like infrared IR scene simulation is the use of large quantities of uncorrelated random numbers. It is therefore of interest to have a fast uniform random number generator implemented in reconfigurable hardware. While there have been previous attempts to accelerate the MT19937 pseudouniform random number generator using FPGAs we believe that we can substantially improve the previous implementations to develop a higher throughput and more areatime efficient design. Due to the potential for parallel implementation of random numbers generators designs that have both a small area footprint and high throughput are to be preferred to ones that have the high throughput but with significant extra area requirements. In this paper we first present a single port design and then present an enhanced 624 port hardware implementation of the MT19937 algorithm. The 624 port hardware implementation when implemented on a Xilinx XC2VP70-6 FPGA chip has a throughput of X 109 32 bit random numbers per second which is more than 17x that of the previously best published uniform random number generator. Furthermore it has the lowest area time metric of all the currently published FPGA-based pseudouniform random number generators.