Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article Formal Methods for Scheduling of Latency-Insensitive Designs | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2007 Article ID39161 16 pages doi 2007 39161 Research Article Formal Methods for Scheduling of Latency-Insensitive Designs Julien Boucaron Robert de Simone and Jean-Vivien Millo Aoste project-team INRIA Sophia-Antipolis 2004 rouye des lucioles BP 93 06902 Sophia Antipolis Cedex France Received 1 July 2006 Revised 23 January 2007 Accepted 11 May 2007 Recommended by Jean-Pierre Talpin Latency-insensitive design LID theory was invented to deal with SoC timing closure issues by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behavior is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements relay-stations RS and shell-wrappers SW . Our first goal is to provide a formal modeling of RS and SW that can be then formally verified. As turns out resulting behavior is fc-periodic thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs throughput equalization adding integer latencies wherever possible residual cases require introduction of fractional registers FRs at specific locations. Benchmark results are presented run on our Kpassa tool implementation. Copyright 2007 Julien Boucaron et al. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. 1. INTRODUCTION Long wire interconnect latencies induce time-closure difficulties in modern SoC designs with propagation of signals across the die in a single clock cycle being problematic. The theory of latency-insensitive design LID proposed originally by Carloni et al. 1 2 offers solutions for this issue. This theory can roughly be described as such
