Fvixed-Point Configurable Hardware Components | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2006 Article ID 23197 Pages 1-13 DOI ES 2006 23197 Fixed-Point Configurable Hardware Components Romuald Rocher Daniel Menard Nicolas Herve and Olivier Sentieys ENSSAT Universite de Rennes 1 6 rue de Kerampont 22305 Lannion IRISA Universite de Rennes 1 Campus de Beaulieu 35042 Rennes France Received 1 December 2005 Revised 4 April 2006 Accepted 8 May 2006 To reduce the gap between the VLSI technology capability and the designer productivity design reuse based on IP intellectual properties is commonly used. In terms of arithmetic accuracy the generated architecture can generally only be configured through the input and output word lengths. In this paper a new kind of method to optimize fixed-point arithmetic IP has been proposed. The architecture cost is minimized under accuracy constraints defined by the user. Our approach allows exploring the fixed-point search space and the algorithm-level search space to select the optimized structure and fixed-point specification. To significantly reduce the optimization and design times analytical models are used for the fixed-point optimization process. Copyright 2006 Romuald Rocher et al. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. 1. INTRODUCTION Advances in VLSI technology offer the opportunity to integrate hardware accelerators and heterogenous processors in a single chip system-on-chip or to obtain FPGAs with several millions of gate equivalent. Thus complex signal processing applications can be now implemented in embedded systems. For example the third generation of mobile communication system requires implementing in a digital platform the wide band code division multiple access WCDMA transmitter receiver a turbo-decoder and different codecs for voice AMR image JPEG and video
