Báo cáo hóa học: " Design and Characterization of a 5.2 GHz/2.4 GHz ΣΔ Fractional-N Frequency Synthesizer for Low-Phase Noise Performance"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Design and Characterization of a GHz/ GHz ΣΔ Fractional-N Frequency Synthesizer for Low-Phase Noise Performance | Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006 Article ID 48489 Pages 1-11 DOI WCN 2006 48489 Design and Characterization of a GHz GHz XA Fractional-N Frequency Synthesizer for Low-Phase Noise Performance John W. M. Rogers 1 Foster F. Dai 2 Calvin Plett 1 and MarkS. Cavin3 1 Carleton University 1125 Colonel Drive Ottawa ON Canada K1S 5B6 2 Electrical and Computer Engineering Department Auburn University Auburn AL 36849-5201 USA 3Alereon Inc. 7600 North Capital of Texas Highway Building C Suite 200 Austin TX 78731 USA Received 8 August 2005 Revised 8 January 2006 Accepted 13 January 2006 This paper presents a complete noise analysis of a XA-based fractional-N phase-locked loop PLL based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally predicted and measured phase jitter showed good agreement. For an LO frequency of GHz predicted and measured phase noise was rms and rms respectively. Copyright 2006 John W. M. Rogers et al. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. 1. INTRODUCTION High-speed frequency synthesis is one of the most challenging areas in radio frequency integrated circuit RFIC design. It requires diverse knowledge of both high-speed analog and digital circuits as well as deep knowledge of system level issues. The performance requirements on circuits used for frequency synthesis are often extremely demanding making the design of these blocks even more challenging. .

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