Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: A Visual Environment for Real-Time Image Processing in Hardware (VERTIPH) | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2006 Article ID 72962 Pages 1-8 DOI ES 2006 72962 A Visual Environment for Real-Time Image Processing in Hardware VERTIPH C. T. Johnston D. G. Bailey and P. Lyons Institute of Information Sciences and Technology Massey University Private Bag 11222 Palmerston North 4442 New Zealand Received 14 December 2005 Revised 4 May 2006 Accepted 28 May 2006 Real-time video processing is an image-processing application that is ideally suited to implementation on FPGAs. We discuss the strengths and weaknesses of a number of existing languages and hardware compilers that have been developed for specifying image processing algorithms on FPGAs. We propose VERTIPH a new multiple-view visual language that avoids the weaknesses we identify. A VERTIPH design incorporates three different views each tailored to a different aspect of the image processing system under development an overall architectural view a computational view and a resource and scheduling view. Copyright 2006 C. T. Johnston et al. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. 1. INTRODUCTION FPGAs field programmable gate arrays are ideal in many embedded systems applications because they have several desirable attributes small size low-power consumption a large number of I O ports and a large number of computational logic blocks. As they have grown in size and functionality there has been increasing interest in using them as implementation platforms for image processing applications particularly real-time video processing 1 . Images have a high degree of spatial parallelism and thus image processing applications are ideally suited to implementation on FPGAs which contain large arrays of parallel logic and registers and can support pipelined algorithms. However there is a .
