Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2007 Article ID 71794 10 pages doi 2007 71794 Research Article Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines Johannes Furtler 1 Peter Rossler 2 Jorg Brodersen 1 Herbert Nachtnebel 3 Konrad J. Mayer 1 Gerhard Cadek 4 and Christian Eckel4 1 Business Unit of High Performance Image Processing Austrian Research Centers Gmbh ARC 2444 Seibersdorf Austria 2 Department of Embedded Systems University of Applied Sciences Hochstadtplatz 5 1200 Vienna Austria 3 Institute of Computer Technology Vienna University of Technology Gufhausstrafe 27-29 E384 1040 Vienna Austria 4 Oregano Systems - Design and Consulting GesmbH Phorusgasse 8 1040 Vienna Austria Received 1 May 2006 Revised 21 September 2006 Accepted 9 October 2006 Recommended by Udo Kebschull This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed high-resolution cameras. Due to performance requirements some functionality has been implemented on dedicated hardware based on a field programmable gate array FPGA which is coupled to a high-end digital signal processor DSP . The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA including low-level image processing algorithms flat-field correction image pyramid generation neighborhood operations and advanced processing units programmable arithmetic unit geometry unit . Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results. Copyright 2007 Johannes Furtler et al. This is an open access article distributed under
