Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Bit Manipulation Accelerator for Communication Systems Digital Signal Processor | EURASIP Journal on Applied Signal Processing 2005 16 2655-2663 2005 Hindawi Publishing Corporation Bit Manipulation Accelerator for Communication Systems Digital Signal Processor Sug H. Jeong School of Electrical and Computer Engineering Ajou University Suwon 443-749 Korea Email jshajou@ Myung H. Sunwoo School of Electrical and Computer Engineering Ajou University Suwon 443-749 Korea Email sunwoo@ Seong K. Oh School of Electrical and Computer Engineering Ajou University Suwon 443-749 Korea Email oskn@ Received 30 January 2004 Revised 14 November 2004 This paper proposes application-specific instructions and their bit manipulation unit BMU which efficiently support scrambling convolutional encoding puncturing interleaving and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR exclusive-OR operations and bit insertion extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC Mm standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40 80 for scrambling convolutional encoding and interleaving compared with existing DSPs. Keywords and phrases bit manipulation application-specific DSP VLSI architecture. 1. INTRODUCTION With the rapid progress of communication technologies various communication systems have been developed such as xDSL digital subscriber line WLAN wireless local area network PLC power-line communications DMB digital multimedia broadcasting and IMT-2000 International Mobile Telecommunications-2000 . These communication systems require large computational power and low power consumption. Therefore ASIC application-specific integrated circuit solutions have been widely used to implement these communication systems. However conventional ASIC chips face several limitations such as lack of flexibility for various .
