Various efficient VHDL behavioural modelling language constructs are available to generate stimulus to test a VHDL model, ., • for loop • defining stimulus array & indexing the array to apply stimulus • reading stimulus data directly from a file Messages can also be added to testbench Remember that this type of testbench / behavioural VHDL code is not intended for logic synthesis, and normally cannot be synthesised ! Refer to muxAndDecEx1 lab files for these examples of testbench coding.
