Increased miniaturization of the integrated chip has largely been responsible for the rapid advances in semiconductor device performance, driving the industry’s growth over the past decade(s). Soon the minimum feature size in a typical integrated circuit device will be well below 100 nm. At these dimensions, interlayers with extremely low dielectric constants (k) are imperative to reduce the cross-talk between adjacent lines and also enhance device speed. State-of-the-art non-porous, silicon-based low-k dielectric materials have k values on the order of
