The advances in ultra-large-scale integration (ULSI) technology mainly have been based on downscaling of the minimum feature size of complementary metal-oxide semiconductor (CMOS) transistors. The limit of scaling is approaching and there are unsolved problems such as the number of electrons in the device’s active region. If this number is reduced to less than 10 electrons (or holes), quantum fluctuation errors will occur and the gate insulator thickness will become too small to block quantum mechanical tunneling, which may result in unacceptably large leakage currents
