In the MEMS industry, systems for deep reactive-ion etching (DRIE) utilize fast pumping, fast-response mass-flow controllers inductive coupling of power, and heated chamber and pump lines that are critical to achieve reliable etch rates. In contrast, we have achieved 8:1 aspect-ratio PhC structures with 62nm vertica membrane walls using a standard reactive-ion etching process based on a sidewall passivation processes. In the remainder of this section we discuss this fabrication process. To begin we use SOI wafers manufactured by SOITEC that consis of two different SOI wafers: one consisting of a silicon device layer (waveguide core) with a 1µm SiO2 insulator layer supported by a bulk silicon.
