8-bit CPU optimized for control applications Extensive Boolean processing (single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space Up to 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bi-directional and individually addressable I/O lines Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels | 8051 Core Specification Outlines Introduction Architecture Operation Registers Introduction MCS-51 family, originally designed by Intel in the 1980’s Used in a large percentage of embedded systems Includes several on-chip peripherals, like timers and counters 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory Features (1/2) 8-bit CPU optimized for control applications Extensive Boolean processing (single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space Up to 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bi-directional and individually addressable I/O lines Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels Features (2/2) Outlines Introduction Architecture Operation Registers Architecture Memory Organization CPU Clock Interrupt Structure Port Structures Timer/Counters Reset Memory Organization (1/3) Logical separation of program and data memory Separate address spaces for Program (ROM) and Data (RAM) Memory Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU Program Memory Only be read, not written to The address space is 16-bit, so maximum of 64K bytes Up to 4K bytes can be on-chip (internal) of 8051 core PSEN (Program Store Enable) is used for access to external Program Memory Memory Organization (2/3) Data Memory Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions There is also a number of Special Function Registers (SFRs) Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions External memory of maximum 64K bytes is accessible by “movx” Memory Organization (3/3) Internal Data Memory, 128 bytes CPU Clock 8051 microcontroller has a clock input pin Interrupt Structure The 8051 provides 4 interrupt sources Two external interrupts Two timer interrupts Additional . | 8051 Core Specification Outlines Introduction Architecture Operation Registers Introduction MCS-51 family, originally designed by Intel in the 1980’s Used in a large percentage of embedded systems Includes several on-chip peripherals, like timers and counters 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory Features (1/2) 8-bit CPU optimized for control applications Extensive Boolean processing (single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space Up to 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bi-directional and individually addressable I/O lines Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels Features (2/2) Outlines Introduction Architecture Operation Registers Architecture Memory Organization CPU Clock Interrupt Structure Port Structures Timer/Counters Reset Memory Organization (1/3) Logical separation of program and data memory Separate address .