Flash microcontroller Architectural Overview Features8: Bit CPU Optimized for Control Applications, Extensive Boolean Processing Capabilities, On-Chip Flash Program Memory, On-Chip Data RAM,. | Features • 8-Bit CPU Optimized for Control Applications • Extensive Boolean Processing Capabilities (Single-Bit Logic) • On-Chip Flash Program Memory • On-Chip Data RAM • Bidirectional and Individually Addressable I/O Lines • Multiple 16-Bit Timer/Counters • Full Duplex UART • Multiple Source/Vector/Priority Interrupt Structure • On-Chip Clock Oscillator • On-chip EEPROM (AT89S series) • SPI Serial Bus Interface (AT89S Series) • Watchdog Timer (AT89S Series) The basic architectural structure of the AT89C51 core is shown in Figure 1. Flash Microcontroller Architectural Overview Block Diagram Figure 1. Block Diagram of the AT89C core EXTERNAL INTERRUPTS ETC. ON-CHIP FLASH TIMER 1 ON-CHIP RAM INTERRUPT CONTROL TIMER 0 COUNTER INPUTS CPU OSC BUS CONTROL 4 I/O PORTS SERIAL PORT TXD P0 P2 P1 P3 RXD ADDRESS/DATA For more information on the individual devices and features, refer to the Hardware Descriptions and Data Sheets of the specific device. 0497B-B–12/97 2-3 Figure 2. Block Diagram of the AT89S core Figure 3. AT89C51/LV51 and AT89C52/LV52 Memory Structure PROGRAM MEMORY (READ ONLY) FFFFH: DATA MEMORY (READ/WRITE) FFFFH: EXTERNAL EXTERNAL INTERNAL FFH: EA = 0 EXTERNAL EA = 1 INTERNAL 0000 00 0000 PSEN RD WR 2-4 Architectural Overview Architectural Overview Reduced Power Modes To exploit the power savings available in CMOS circuitry, Atmel’s Flash microcontrollers have two software-invoked reduced power modes. • Idle Mode. The CPU is turned off while the RAM and other on-chip peripherals continue operating. In this mode, current draw is reduced to about 15 percent of the current drawn when the device is fully active. • Power Down Mode. All on-chip activities are suspended, while the on-chip RAM continues to hold its data. In this mode, the device typically draws less than 15 µA, and can be as low as µA. In addition, these devices are designed using static logic, which does not require continuous clocking. That is, the clock frequency can be slowed or even stopped
