This manual describes the Verilog portion of Synopsys FPGA Compiler II/FPGA Expressapplication, part of the Synopsys suite of synthesis tools. FPGA Compiler II/FPGA Expressreads an RTL Verilog HDL model of a discrete electronic system and synthesizes this description into a gate-level netlist. FPGA Compiler II/FPGA Expresssupports of the Verilog language. Deviations from the definition of the Verilog language are explicitly noted. Constructs added in versions subsequent to Verilog might not be supported. Aspects of the Verilog language that are not supported are listed in Appendix B.
