Cùng tìm hiểu CPU Structure; CPU With Systems Bus; CPU Internal Structure;. được trình bày cụ thể trong "Bài giảng Computer Organization and Architecture: Chapter 12 - CPU Structure and Function". | William Stallings Computer Organization and Architecture 6th Edition Chapter 12 CPU Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data 22 CPU With Systems Bus CPU Internal Structure Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy 23 User Visible Registers General Purpose Data Address Condition Codes 24 General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data Accumulator Addressing Segment 25 General Purpose Registers (2) Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity Make them specialized Smaller (faster) instructions Less flexibility 26 How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and | William Stallings Computer Organization and Architecture 6th Edition Chapter 12 CPU Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data 22 CPU With Systems Bus CPU Internal Structure Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy 23 User Visible Registers General Purpose Data Address Condition Codes 24 General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data Accumulator Addressing Segment 25 General Purpose Registers (2) Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity Make them specialized Smaller (faster) instructions Less flexibility 26 How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC 27 How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double int a; long int a; 28 Condition Code Registers Sets of individual bits . result of last operation was zero Can be read (implicitly) by programs . Jump if zero Can not (usually) be set by programs 29 Control & Status Registers Program Counter Instruction Decoding Register Memory Address Register Memory Buffer Register Revision: what do these all do? 30 Program Status Word A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor 31 Supervisor Mode Intel ring zero Kernel mode Allows privileged instructions to execute Used by operating system Not available to user programs 32 Other Registers May have registers pointing to: Process control blocks (see O/S) Interrupt Vectors (see O/S) . CPU design and operating system design are .
