Bài giảng Computer Organization and Architecture: Chapter 15 - IA-64 Architecture hướng đến giới thiệu về Background to IA-64; Motivation; Superscalar v IA-64; Why New Architecture;. | William Stallings Computer Organization and Architecture 6th Edition Chapter 15 IA-64 Architecture Background to IA-64 Pentium 4 appears to be last in x86 line Intel & Hewlett-Packard (HP) jointly developed New architecture 64 bit architecture Not extension of x86 Not adaptation of HP 64bit RISC architecture Exploits vast circuitry and high speeds Systematic use of parallelism Departure from superscalar Motivation Instruction level parallelism Implicit in machine instruction Not determined at run time by processor Long or very long instruction words (LIW/VLIW) Branch predication (not the same as branch prediction) Speculative loading Intel & HP call this Explicit Parallel Instruction Computing (EPIC) IA-64 is an instruction set architecture intended for implementation on EPIC Itanium is first Intel product Superscalar v IA-64 Why New Architecture? Not hardware compatible with x86 Now have tens of millions of transistors available on chip Could build bigger cache Diminishing . | William Stallings Computer Organization and Architecture 6th Edition Chapter 15 IA-64 Architecture Background to IA-64 Pentium 4 appears to be last in x86 line Intel & Hewlett-Packard (HP) jointly developed New architecture 64 bit architecture Not extension of x86 Not adaptation of HP 64bit RISC architecture Exploits vast circuitry and high speeds Systematic use of parallelism Departure from superscalar Motivation Instruction level parallelism Implicit in machine instruction Not determined at run time by processor Long or very long instruction words (LIW/VLIW) Branch predication (not the same as branch prediction) Speculative loading Intel & HP call this Explicit Parallel Instruction Computing (EPIC) IA-64 is an instruction set architecture intended for implementation on EPIC Itanium is first Intel product Superscalar v IA-64 Why New Architecture? Not hardware compatible with x86 Now have tens of millions of transistors available on chip Could build bigger cache Diminishing returns Add more execution units Increase superscaling “Complexity wall” More units makes processor “wider” More logic needed to orchestrate Improved branch prediction required Longer pipelines required Greater penalty for misprediction Larger number of renaming registers required At most six instructions per cycle Explicit Parallelism Instruction parallelism scheduled at compile time Included with machine instruction Processor uses this info to perform parallel execution Requires less complex circuitry Compiler has much more time to determine possible parallel operations Compiler sees whole program General Organization Key Features Large number of registers IA-64 instruction format assumes 256 128 * 64 bit integer, logical & general purpose 128 * 82 bit floating point and graphic 64 * 1 bit predicated execution registers (see later) To support high degree of parallelism Multiple execution units Expected to be 8 or more Depends on number of transistors available Execution of parallel .
