'Intel’s ‘cmpxchg’ instruction Review of the i386 registers, The x86 ‘system’ registers, Intel’s documentation, Instruction format, ‘cmpxchg’ description, An instruction-instance, The complete function. | Intel’s ‘cmpxchg’ instruction How does the Linux kernel’s ‘cmos_lock’ mechanism work? Review of the i386 registers EAX CS EBX DS ECX ES EDX FS ESI GS EDI SS EBP ESP General Registers (32-bits) Segment Registers (16-bits) EIP EFLAGS Program Control and Status Registers (32 bits) The x86 ‘system’ registers CR0 DR0 CR1 DR1 CR2 DR2 CR3 DR3 CR4 DR4 CR5 DR5 CR6 DR6 (16-bits) CR7 DR7 Control Registers (32-bits) Debug Registers (32-bits) LDTR TR means ‘unimplemented’ GDTR IDTR (48-bits) How often is ‘cmpxchg’ used? $ cat | grep cmpxchg c01046de: c0105591: c01055d9: c010b895: c010b949: c0129a9f: c0129acf: c012d377: c012d41a: c012d968: c012e568: c012e57a: c012e58a: c012e83f: c012e931: c012ea94: c012ecf4: c012f08e: c012f163: c013cb60: c0148b3c: c0150d0f: c0150d87: c0199c5e: c024b06f: c024b2fe: c024b321: c024b34b: c024b960: f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 f0 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 15 15 15 11 0b 0b 0b 0e 0e 16 2e 2e 2e 13 0a 11 13 4b 11 0e 29 3b 31 0b 0b 51 51 4b 53 3c 99 30 3c 99 30 3c 99 .
