Detecting PCI devices: On identifying the peripheral equipment installed in our PC present Early PCs, the PC’s evolution, PCI Configuration Space, PCI Configuration Header, Three IA-32 address-spaces, Interface to PCI Configuration Space. | Detecting PCI devices On identifying the peripheral equipment installed in our PC Early PCs • Peripheral devices in the early PCs used fixed i/o-ports and fixed memory-addresses, .: – – – – – – – – Video memory address-range: 0xA0000-0xBFFFF Programmable timer i/o-ports: 0x40-0x43 Keyboard and mouse i/o-ports: 0x60-0x64 Real-Time Clock’s i/o-ports: 0x70-0x71 Hard Disk controller’s i/o-ports: 0x01F0-01F7 Graphics controller’s i/o-ports: 0x03C0-0x3CF Serial-port controller’s i/o-ports: 0x03F8-0x03FF Parallel-port controller’s i/o-ports: 0x0378-0x037A The PC’s evolution • It became clear in the 1990s that there would be contention among equipment vendors for ‘fixed’ resource-addresses, which of course were in limited supply • Among the goals that motivated the PCI Specification was the creation of a more flexible scheme for allocating addresses that future peripheral devices could use PCI Configuration Space A non-volatile parameter-storage area for each PCI device-function PCI Configuration Space Header (16 doublewords – fixed format) 64 doublewords PCI Configuration Space Body (48 doublewords – variable format) PCI Configuration Header 16 doublewords 31 0 Status Register BIST Header Type Command Register Latency Timer Cache Line Size 31 0 Device ID Vendor ID Class Code Class/SubClass/ProgIF Revision ID Dwords 1- 0 3- 2 Base Address 1 Base Address 0 5- 4 Base Address 3 Base Address 2 7- 6 Base Address 5 Base Address 4 9- 8 CardBus CIS Pointer 11 - 10 Subsystem Device ID Subsystem Vendor ID reserved capabilities pointer Expansion ROM Base Address 13 - 12 Maximum Minimum Interrupt Latency Grant Pin Interrupt Line reserved 15 - .
