Lecture Introduction to computing systems (from bits & gates to C & beyond): Chapter 5 - The LC-2 instruction set architecture. This chapter presents the following content: Operate instructions, data movement instructions, control instructions. | Chapter 5 The LC-2 Instruction Set Architecture Operate instructions Data Movement instructions Control Instructions ISA Overview Memory Address space Addressability: Word or Byte Registers Number Type Instructions Operations Data Types Addressing Modes 5 - LC-2 Memory Organization addressability word (16 bits/location) address space 216 locations = 64k 29 words/page = 512 27 pages =128 page location in page [8:0] [15:9] Address [16:0] 5 - General Purpose Registers (GPRs) Registers Special “memory” that is “inside” the CPU Very fast access: 1 clock cycle. General Purpose Registers: addressable by an instrcution (visible to the user). Other registers may not be accessible (not architectured) LC-2 8 general purpose registers: R0,R1,.,R7 a register can hold any 16 bit pattern - . data or addresses Other special purpose registers (later) 5 - Instructions Two main parts Opcode: specifies what the instruction does. Operand(s): what the instruction acts on Instruction sets can be complex or simple LC-2 4-bit opcode => 16 instructions up to two sources and one destination Example: 0 0 0 1 0 1 1 0 0 1 0 1 0 0 0 0 ADD R3 R1 R4 15 14 13 12 11 10 9 8 7 6 5 2 1 0 4 3 5 - Operations Operate Manipulate data directly ADD, AND, NOT Data Movement Move data between memory and registers (CPU) LD, LDI, LDR, LEA, ST, STI, STR Control Change the sequence of instruction execution BR, JMP/JSR, JMPR/JSSR, RET, RTI, TRAP 5 - Data Types What data types are supported by the computer instructions? Eg. integer, floating point, BCD, character . LC-2: only 2's complement integers bit strings and addresses are not data types 5 - Condition Codes 3 single-bit registers (set to 1 or cleared to 0) N: value written was negative Z: value written was zero P: value written was positive Affected each time any register is written Condition codes are read by conditional branch instructions 5 - Addressing Modes - 1 Where is the operand? The addressing modes provide multiple . | Chapter 5 The LC-2 Instruction Set Architecture Operate instructions Data Movement instructions Control Instructions ISA Overview Memory Address space Addressability: Word or Byte Registers Number Type Instructions Operations Data Types Addressing Modes 5 - LC-2 Memory Organization addressability word (16 bits/location) address space 216 locations = 64k 29 words/page = 512 27 pages =128 page location in page [8:0] [15:9] Address [16:0] 5 - General Purpose Registers (GPRs) Registers Special “memory” that is “inside” the CPU Very fast access: 1 clock cycle. General Purpose Registers: addressable by an instrcution (visible to the user). Other registers may not be accessible (not architectured) LC-2 8 general purpose registers: R0,R1,.,R7 a register can hold any 16 bit pattern - . data or addresses Other special purpose registers (later) 5 - Instructions Two main parts Opcode: specifies what the instruction does. Operand(s): what the instruction acts on Instruction sets .
