Lecture VLSI Digital signal processing systems - Chapter 17: Low-power design includes content as: VLSI digital signal processing systems, power consumption in DSP, power dissipation, CMOS power consumption, dynamic power consumption, switching activity (α), increased switching activity due to glitching, | Chapter 17: Low-Power Design Keshab K. Parhi and Viktor Owall Speed Complexity IC Design Space Chapter 17 Power Sp ee Area d New Design Space 2 VLSI Digital Signal Processing Systems • Technology trends: – 200-300M chips by 2010 ( micron CMOS) • Challenges: – – – – – – – Chapter 17 Low-power DSP algorithms and architectures Low-power dedicated / programmable systems Multimedia & wireless system-driven architectures Convergence of Voice, Video and Data LAN, MAN, WAN, PAN Telephone Lines, Cables, Fiber, Wireless Standards and Interoperability 3 Power Consumption in DSP • Low performance portable applications: – Cellular phones, personal digital assistants – Reasonable battery lifetime, low weight • High performance portable systems: – Laptops, notebook computers • Non-portable systems: – Workstations, communication systems – DEC alpha: 1 GHz, 120 Watts – Packaging costs, system reliability Chapter 17 4 Power Dissipation Two measures are important • Peak power (Sets dimensions) Ppeak = VDD × iDDmax • Average power (Battery and cooling) T VDD iDD (t) dt Pav = T 0 Chapter .
