Bài giảng Thiết kế vi mạch số: Chương 5 - TS. Trương Quang Vinh

Bài giảng "Thiết kế vi mạch số - TS. Trương Quang Vinh"trình bày định nghĩa chậm trễ, các mô hình trễ RC và các mô hình trễ tuyến tính. . | Lecture 5: Delay 1. 2. 3. 4. Delay definition Transient response RC delay models Linear delay models 1. Delay Definitions tpdr: rising propagation delay – From input to rising output crossing VDD/2 tpdf: falling propagation delay – From input to falling output crossing VDD/2 tpd: average propagation delay – tpd = (tpdr + tpdf)/2 tr: rise time – From output crossing VDD to VDD tf: fall time – From output crossing VDD to VDD 5: DC and Transient Response CMOS VLSI Design 4th Ed. 2 1 1. Delay Definitions tcdr: rising contamination delay – From input to rising output crossing VDD/2 tcdf: falling contamination delay – From input to falling output crossing VDD/2 tcd: average contamination delay – tpd = (tcdr + tcdf)/2 5: DC and Transient Response CMOS VLSI Design 4th Ed. 3 Arrival time Arrival time is the latest time at which each node in a block of logic will switch The slack is the difference between the required and arrival times. Positive slack means that the circuit meets timing. Negative slack means that the circuit is not fast enough. 5: DC and Transient Response CMOS VLSI Design 4th Ed. 4 2 2. Transient Response DC analysis tells us Vout if Vin is constant Transient analysis tells us Vout(t) if Vin(t) changes – Requires solving differential equations Input is usually considered to be a step or ramp – From 0 to VDD or vice versa 5: DC and Transient Response CMOS VLSI Design 4th Ed. 5 DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter – When Vin = 0 -> Vout = VDD – When Vin = VDD -> Vout = 0 VDD – In between, Vout depends on Idsp transistor size and current Vin Vout – By KCL, must settle such that Idsn Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight 5: DC and Transient Response CMOS VLSI Design 4th Ed. 6 3 Transistor Operation Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in – Cutoff? – Linear? – Saturation? 5: DC and Transient .

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