Chapter 6 explains the realization of VHDL operators and data types, provides an in-depth overview on the synthesis process and discusses the timing issue involved in synthesis. | Synthesis Of VHDL Code RTL Hardware Design Chapter 6 1 Outline 1. 2. 3. 4. 5. Fundamental limitation of EDA software Realization of VHDL operator Realization of VHDL data type VHDL synthesis flow Timing consideration RTL Hardware Design Chapter 6 2 1. Fundamental limitation of EDA software • Can “C-to-hardware” be done? • EDA tools: – Core: optimization algorithms – Shell: wrapping • What does theoretical computer science say? – Computability – Computation complexity RTL Hardware Design Chapter 6 3 Computability • A problem is computable if an algorithm exists. • ., “halting problem”: – can we develop a program that takes any program and its input, and determines whether the computation of that program will eventually halt? • any attempt to examine the “meaning” of a program is uncomputable RTL Hardware Design Chapter 6 4 Computation complexity • How fast an algorithm can run (or how good an algorithm is)? • “Interferences” in measuring execution time: – types of CPU, speed of CPU, compiler etc. RTL Hardware Design Chapter .
