This chapter covers the syntax, usage and implementation of concurrent signal assignment statements of VHDL. It shows how to realize these constructs by multiplexing and priority routing networks. | Concurrent Signal Assignment Statements RTL Hardware Design Chapter 4 1 Outline 1. 2. 3. 4. 5. Combinational versus sequential circuit Simple signal assignment statement Conditional signal assignment statement Selected signal assignment statement Conditional vs. selected signal assignment RTL Hardware Design Chapter 4 2 1. Combinational vs. sequential circuit • Combinational circuit: – No internal state – Output is a function of inputs only – No latches/FFs or closed feedback loop • Sequential circuit: – With internal state – Output is a function of inputs and internal state • Sequential circuit to be discussed later RTL Hardware Design Chapter 4 3 2. Simple signal assignment statement RTL Hardware Design Chapter 4 4 • Simple signal assignment is a special case of conditional signal assignment • Syntax: signal_name <= projected_waveform; • ., y <= a + b + 1 after 10 ns; • Timing info ignored in synthesis and δ-delay is used: signal_name <= value_expression RTL Hardware Design Chapter .
