In this paper these features and approach has been elaborated using the example of DLX® ALU at a basic level. The ALU is designed using Verilog® HDL and a model has been extracted with the help Xilinx® System Generator® for MATLAB®. Later hardware implementation of the design is done on FPGA. | ISSN:2249-5789 Kapil Kumar et al, International Journal of Computer Science & Communication Networks,Vol 2(2), 231-235 Implementation of DLX based ALU Using Xilinx® System Generator® Kapil Kumar#1, Shamim Akhter#2, Shivam Gupta#3 Department of Electronics & Communication Engineering Jaypee Institute of Information & Technology, India kapil10305171mtech@, shamimsf@, shivam8102255ece@ Abstract- In today’s fast paced growing embedded industry, design’s complexity has increased and hence designers must have extensive knowledge of various design and modeling aspects. In this context, Xilinx® System Generator® provides efficient ways to design and analyze the complex systems in real time, which may also be realized on reconfigurable devices like FPGA. Xilinx® System Generator includes applications like extraction of MATLAB® models from HDL designs and to simulate these in linking with HDL simulators. In this paper these features and approach has been elaborated using the example of DLX® ALU at a basic level. The ALU is designed using Verilog® HDL and a model has been extracted with the help Xilinx® System Generator® for MATLAB®. Later hardware implementation of the design is done on FPGA. block which is directly implemented on FPGA, hence provided an easy method for simulating and implementing complex system. Its also provides an interface for incorporating HDL based implementation in our design. In this case one will get benefit by designing the system using HDL like Verilog [7]. Integration of Simulink model and a HDL model gives benefit in terms of complexity, reusability, and analysis and hardware implementation of a system. In this paper an approach has been illustrated for the same In this paper, section II and III deals with DLX based ALU [2] design using Verilog HDL. The specifications and architectural description of DLX based ALU is also given. In section IV, design steps are shown to extract the Xilinx Block model from
