This paper presents hardware implementation of a five image enhancement algorithms in spatial domain using FPGA technology. These algorithms are: median filter, contrast stretching, histogram equalization, negative image transformation and power-law transformation. | ISSN:2249-5789 Tarek M Bittibssi et al , International Journal of Computer Science & Communication Networks,Vol 2(4), 536-542 Image Enhancement Algorithms using FPGA 1 2 3 Tarek M. Bittibssi , Gouda I. Salama , Yehia Z. Mehaseb and Adel E. Henawy 1& 4 2&3 4 Dept. of ECE, Ain Shams University, Cairo, Egypt Dept. of ECE, Military Technical College, Cairo, Egypt Abstract Image Enhancement techniques can be classified into two categories as spatial domain and frequency domain. This paper presents hardware implementation of a five image enhancement algorithms in spatial domain using FPGA technology. These algorithms are: median filter, contrast stretching, histogram equalization, negative image transformation and power-law transformation. All algorithms are studied and hardware circuits are realized for them. Then hardware is modeled using Altera System and synthesized onto Cyclon III on Development kit (DE0) FPGA chip. Keywords: Image Enhancement, FPGA I. INTRODUCTION Image enhancement is the processing of images to improve their appearance to human viewers or to enhance other image processing systems performance. Methods and objectives vary with the application. When images are enhanced for human viewers, as in television, the objective may be to improve perceptual aspects: image quality, intelligibility, or visual appearance. In other applications, such as object identification by machine, an image may be preprocessed to aid machine performance. Because the objective of image enhancement is dependent on the application context, and the criteria for enhancement are often subjective or too complex to be easily converted to useful objective measures, image enhancement algorithms tend to be simple, qualitative, and disambiguation In [1], S. Sowmya , Roy Paily addresses the implementation of image enhancement algorithms like brightness control, contrast adjustment and histogram equalization on FPGA. The minimum period to the implemented algorithms is 5 ns for .
