This research work includes TSPICE simulation of encoder based on modified boundary shift coding used to reduce inductance dominant crosstalk in coupled RLC modeled interconnects. | ISSN:2249-5789 Hitlendra Pratap Singh et al , International Journal of Computer Science & Communication Networks,Vol 2(5), 596-600 Crosstalk and Crosstalk Delay Minimization in On-Chip DSM VLSI Interconnects Hitlendra Pratap Singh1, Rajesh Mehra2 1 Dept. of ECE, MIET Group of Institutions, Meerut, India-250001 2 Dept. of ECE, NITTTR, Chandigarh, India-160019 Abstract In On-chip DSM and UDSM VLSI Circuits because of increase device densitities and operating clock frequency the crosstalk noise, crosstalk induced delay, interconnect delay , signal integrity affect the performance and reliability of the chip. Due to increase in operating frequency beyond GHz range inductive effects are dominant over capacitive effect. Therefore, the coding methods used in RC Modeled are not suitable in high frequency application circuits. This research work includes TSPICE simulation of encoder based on modified boundary shift coding used to reduce inductance dominant crosstalk in coupled RLC modeled interconnects. Keywords- Crosstalk, Crosstalk Delay, Interconnect delay, Boundary shift Code, Inductive effects I. INTRODUCTION As VLSI technology has marched into the DSM/UDSM regime, bus based interconnect has become bottleneck in Onchip systems. In SoC designs where wide and long buses are used interconnect delays dominate over device delay. The crosstalk in on-chip buses is highly dependent on the data patterns transmitted on the bus [10]. On-chip interconnect delay also suffers from various kind of DSM noise sources like power-grid fluctuations, electromagnetic noise, and alpha particle radiation. Defects in manufacturing also cause an unavoidable error in the systems. These induced errors generates serious data transmission reliability concerns for interconnects. Therefore, errorcorrection scheme is required for on-chip interconnects [2, 11]. In on-chip due to low operating clock frequency mainly source of noise is parasitic capacitance and interconnect can be modeled as RC .
