Non-binary low-density parity-check (NBLDPC) codes have a better error-correcting performance in comparison with their binary counterparts when the code length is moderate. However, NB-LDPC decoding is high complexity, especially the check node processing. In this paper, a novel check node processing algorithm and corresponding architectures are proposed for the trellis min-max NB-LDPC decoding to reduce the hardware complexity. A layered decoder architecture is implemented for the (2304, 2048) NB-LDPC code over GF(16) based on the proposed algorithm with a 90-nm CMOS technology. |
