Basic Concepts part 3

[ Team LiB ] System Tasks and Compiler Directives In this section, we introduce two special concepts used in Verilog: system tasks and compiler directives. System Tasks Verilog provides standard system tasks for certain routine operations. | Team LiB System Tasks and Compiler Directives In this section we introduce two special concepts used in Verilog system tasks and compiler directives. System Tasks Verilog provides standard system tasks for certain routine operations. All system tasks appear in the form keyword . Operations such as displaying on the screen monitoring values of nets stopping and finishing are done by system tasks. We will discuss only the most useful system tasks. Other tasks are listed in Verilog manuals provided by your simulator vendor or in the IEEE Standard Verilog Hardware Description Language specification. Displaying information display is the main system task for displaying values of variables or strings or expressions. This is one of the most useful tasks in Verilog. Usage display p1 p2 p3 . pn pl p2 p3 . pn can be quoted strings or variables or expressions. The format of display is very similar to printf in C. A display inserts a newline at the end of the string by default. A display without any arguments produces a newline. Strings can be formatted using the specifications listed in Table 3-4. For more detailed specifications see IEEE Standard Verilog Hardware Description Language specification. Table 3-4. String Format Specifications Format Display d or D b or B s or S h or H c or C m or M v or V Display variable in decimal Display variable in binary Display string Display variable in hex Display ASCII character Display hierarchical name no argument required Display strength o or O Display variable in octal t or T Display in current time format e or E Display real number in scientific format . 3e10 f or F Display real number in decimal format . g or G Display real number in scientific or decimal whichever is shorter Example 3-3 shows some examples of the display task. If variables contain x or z values they are printed in the displayed string as x or z . Example 3-3 display Task Display the string in quotes display Hello Verilog World -- Hello .