[ Team LiB ] Structured Procedures There are two structured procedure statements in Verilog: always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside | Team LiB Structured Procedures There are two structured procedure statements in Verilog always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structured procedure statements. Verilog is a concurrent programming language unlike the C programming language which is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence. Each always and initial statement represents a separate activity flow in Verilog. Each activity flow starts at simulation time 0. The statements always and initial cannot be nested. The fundamental difference between the two statements is explained in the following sections. initial Statement All statements inside an initial statement constitute an initial block. An initial block starts at time 0 executes exactly once during a simulation and then does not execute again. If there are multiple initial blocks each block starts to execute concurrently at time 0. Each block finishes execution independently of other blocks. Multiple behavioral statements must be grouped typically using the keywords begin and end. If there is only one behavioral statement grouping is not necessary. This is similar to the begin-end blocks in Pascal programming language or the grouping in the C programming language. Example 7-1 illustrates the use of the initial statement. Example 7-1 initial Statement module stimulus reg x y a b m initial m 1 b0 single statement does not need to be grouped initial begin 5 a 1 b1 multiple statements need to be grouped 25 b 1 b0 end initial begin 10 x 1 b0 25 y 1 b1 end initial 50 finish endmodule In the above example the three initial statements start to execute in parallel at time 0. If a delay delay is seen before a statement the statement is executed delay time units after the current simulation time. Thus the execution sequence of the statements inside the initial blocks will be as follows. time 0
