[ Team LiB ] Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, | Team LiB Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters FWIDTH and FDEPTH. For this example the FIFO depth is 4 and the FIFO width is 32 bits. The input output ports of the FIFO are shown in Figure F-1. Figure F-1. FIFO Input Output Ports Input ports All ports with a suffix N are low-asserted. Clk Clock signal RstN Reset signal Data_In 32-bit data into the FIFO FInN Write into FIFO signal FClrN Clear signal to FIFO FOutN Read from FIFO signal Output ports F_Data 32-bit output data from FIFO F_FullN Signal indicating that FIFO is full F_EmptyN Signal indicating that FIFO is empty F_LastN Signal indicating that FIFO has space for one data value F_SLastN Signal indicating that FIFO has space for two data values F_FirstN Signal indicating that there is only one data value in FIFO The Verilog HDL code for the FIFO implementation is shown in Example F-1. Example F-1 Synthesizable FIFO Model FileName Author Venkata Ramana Kalapatapu Company Sand Microelectronics Inc. now a part of Synopsys Inc. Profile Sand develops Simulation Models Synthesizable Cores and Performance Analysis Tools for Processors buses and memory products. Sand s products include models for industry-standard components and custom-developed models for specific simulation environments. define define define FWIDTH FDEPTH FCWIDTH Width of the FIFO. Depth of the FIFO. Counter Width of the FIFO 2 to power 32 4 2 FCWIDTH FDEPTH. module FIFO Clk RstN Data_In FClrN FInN FOutN F_Data F_FullN F_LastN F_SLastN F_FirstN F_EmptyN input input Clk CLK signal. RstN Low Asserted Reset signal. input FWIDTH-1 0 Data_In Data into FIFO. input input input FInN Write into FIFO Signal. FClrN Clear signal to FIFO. FOutN Read from FIFO signal. output FWIDTH-1 0 F_Data FIFO data out. output output output output output F_FullN FIFO full indicating signal. F_EmptyN FIFO empty .